Together with highly increasing integration on one chip currently, usage of memories, mainly Static Random Access Memory (SRAM), applied to wide range of functions is inevitable. However, memory faults are greatly concerned due to purpose of achieving high yield. As a result, a memory built-in self-test (MBIST) has become essential in any system obviously. As regards MBIST, while increasing criteria associating with area, frequency as well as various test algorithms has posed, current approaches have not adapted both such silicon requirements and ability of covering errors with complex algorithms yet. In this work, an effective architecture of MBIST for SRAM type with different configurations is proposed for not only ensuring high ability of detecting memory faults supported by the most popular algorithms namely MARCH C-and TLAPNPSF but also satisfy strict silicon criteria. Indeed, achieving great performance based on necessary experiments on 130nm technology with Application Specific Integrated Circuit (ASIC) design flow has confirmed strong competition to current designs.
|Titel||International Conference on Advanced Computing and Applications (ACOMP), 2016, pp. 121-124.|
|Publikationsstatus||Veröffentlicht - 2016|
|Veranstaltung||2016 International Conference on Advanced Computing and Applications (ACOMP) - |
Dauer: 23 Nov. 2016 → 25 Nov. 2016
|Konferenz||2016 International Conference on Advanced Computing and Applications (ACOMP)|
|Zeitraum||23/11/16 → 25/11/16|
- Data Science