Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an analog IC can be very limited. We leverage the recent advancements in machine learning (ML) and propose two techniques, artificial neural networks (ANN) and Gaussian processes, to learn a surrogate model from an existing test suite. We then explore the surrogate model with Bayesian optimization to guide the generation of additional tests. We use an industrial bandgap case study to evaluate the two approaches and demonstrate the virtue of Bayesian optimization in efficiently generating complementary tests with constrained effort.
|Name||Proceedings - 2022 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2022|
|Konferenz||2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)|
|Zeitraum||7/10/22 → 14/10/22|
- Dependable Systems Engineering