Skip to main navigation Skip to search Skip to main content

A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform

  • Florian Eibensteiner (Speaker)
  • , Jürgen Kogler
  • , Josef Scharinger
    • Johannes Kepler University Linz

    Research output: Chapter in Book or Conference ProceedingsConference Proceedings with Poster Presentationpeer-review

    Original languageEnglish
    Title of host publication2014 IEEE Computer Society Conference on Computer Vision and Pattern Recognition
    Number of pages8
    Publication statusPublished - 2014
    EventIEEE Conference on Computer Vision and Pattern Recognition Workshops, Embedded Vision -
    Duration: 8 Jun 201510 Jun 2015

    Conference

    ConferenceIEEE Conference on Computer Vision and Pattern Recognition Workshops, Embedded Vision
    Period8/06/1510/06/15

    Research Field

    • Former Research Field - Digital Safety and Security

    Cite this